1. Technical Field
This invention relates to integrated circuit devices and a process of making the same, and in particular, this invention relates to microcavity structures which utilize a pinning layer to pin the microcavity structures in selected areas, applications thereof and process of making the same. This invention also relates to the specially shaped contact vias created with the process and the integrated circuit therewith.
2. Related Art
As integrated circuit devices become smaller, spacing between electronic components and conductors becomes ever more critical. Such components and/or conductors are typically separated and isolated by a dielectric material. A vacuum has the best relative dielectric constant (1.0). The dielectric constant of air is just slightly higher than that of a vacuum.
Doped glass is commonly used as an integrated circuit dielectric because its melting point can be made significantly lower than that of regular glass or of other dielectric materials. Boro-Phosphorus Silicate Glass (BPSG) is one exemplary type of doped glass. After deposition over a pattern of polysilicon conductors, for example, a BPSG dielectric layer can be put through a high temperature reflow process, usually at about 900° C., which reflows the BPSG, smooths its surface, and eliminates ‘as deposited’ voids between the polysilicon conductors for facilitating subsequent processing steps.
A typical BPSG material, however, has a significantly higher relative dielectric constant, e.g., about 3.6 to 4.6. One technique which has been used to reduce the relative dielectric constant of BPSG glass is to allow cavities to form in the material at appropriate locations. The cavities can form during the chemical vapor deposition (CVD) process in spaces between raised features, such as conductors or semiconductor mesas. These cavities are essentially air or vacuum filled and therefore constitute a low dielectric constant region between the raised features. In this manner, for example, capacitive coupling between adjacent conductors can be reduced, thereby enhancing device signal speed.
Despite speed improvements, which voids in BPSG films can provide, their proper size and shape formation is presently difficult to control. For example, voids between adjacent conductors are formed when a BPSG layer is deposited on top of a polysilicon conductive pattern. However, during the reflow process, the voids may disappear if the spaces between polysilicon conductors are large enough or the deposited film is thin enough. The voids formed when a BPSG layer of about 7000 Angstroms is deposited over a circuit topography of conductors separated by about 1.0 micron are typically eliminated during reflow. Unfortunately, it is not possible to forgo the reflow process without also losing the smoothness and related benefits such a structure can provide in subsequent processing.
Thus, as with the above-discussed example, there is a need for an improved method for controllably fabricating cavities for semiconductor and micro-machine applications, such as for pressure sensing, chromatography, fabrication of capacitive components, and selectively isolating components and conductors, etc. Further, there is a need for a method to create self-aligned contact vias which do not short circuit to neighboring conductors. Further there is a need to be able to shape contact vias.